Memory management for a hierarchical memory system

ABSTRACT

Disclosed are systems and methods for managing memory. A memory management system may include a table having multiple virtual memory addresses. Each virtual memory address may correspond to a physical memory address and data that identifies a type of memory device corresponding to the physical memory address. The physical memory device can be used to access the memory device when a table hit occurs.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a Continuation of U.S. application Ser. No.16/107,662, entitled “MEMORY MANAGEMENT FOR A HIERARCHICAL MEMORYSYSTEM,” and filed Aug. 21, 2018, which is a Continuation of U.S.application Ser. No. 15/371,044, entitled “MEMORY MANAGEMENT FOR AHIERARCHICAL MEMORY SYSTEM,” and filed Dec. 6, 2016, now U.S. Pat. No.10,089,242 which issued Oct. 2, 2018, which is a Divisional of U.S.application Ser. No. 13/552,491, entitled “MEMORY MANAGEMENT FOR AHIERARCHICAL MEMORY SYSTEM,” and filed Jul. 18, 2012, now U.S. Pat. No.9,524,248 which issued Dec. 20, 2016, the entirety of which areincorporated by reference herein for all purposes.

BACKGROUND Field of Invention

Embodiments of the present invention relate generally to memorymanagement. More specifically, embodiments of the present invention mayprovide one or more techniques for memory management in a hierarchicalmemory system.

Description of Related Art

Computer systems are generally employed in numerous configurations toprovide a variety of computing functions. Processing speeds, systemflexibility, power consumption, and size constraints are typicallyconsidered by design engineers tasked with developing computer systemsand system components. Computer systems generally include a plurality ofmemory devices (e.g., a dual in-line memory module (DIMM) may contain 8,16, or more memory devices, a stacked NAND flash package may contain 2,4, or 8 NAND die) and a plurality of memory types (i.e., memory devicesthat may have different performance and/or power characteristics) whichmay be used to store data (e.g., programs and user data) and which maybe accessible to other system components such as processors orperipheral devices. Such memory devices may include volatile andnon-volatile memory devices.

Typically, the memory address space of a computing system is managed bya memory management system. In certain computing systems, the memorymanagement system may dynamically allocate portions of the memoryaddress space to programs being executed by the processors and mayallocate a separate portion of the memory address space to data beingused by such a program. Conversely, the memory management system maydeallocate portions of the memory address space from programs when theprograms are no longer being executed by the processors. The memorymanagement system may include tables used to map virtual memoryaddresses that are used by the processors to the physical memory addressspace. These tables may include a main memory translation table (MMXT)and a translation lookaside buffer (TLB). Often the TLB contains memorymappings for memory addresses that are used more frequently than thememory addresses in the MMXT. Searching through the MMXT and/or the TLBfor a memory mapping may be time consuming resulting in delayed dataretrieval.

Memory systems are often arranged with a memory hierarchy. For example,certain memory may be found in registers, cache (e.g., level 1, level 2,level 3), main memory (e.g., RAM), disk storage, and so forth. As may beappreciated, some memory systems include memory types that havedifferent operating characteristics (e.g., operate at differing speeds).However, memory management systems generally do not differentiatebetween types of memory in the memory system (e.g., main memory).Accordingly, such memory management systems may handle all types ofmemory in the same manner. Further, some memory devices in the memorysystems may be accessed (e.g., read from and/or written to) a greaternumber of times than other memory devices in the memory systems. Assuch, it may be difficult for a memory management system to identify(e.g., determine) which memory devices operate at a particular speedwithin the memory system. Likewise, it may be difficult for a memorymanagement system to identify which memory devices are accessed morethan others.

Accordingly, embodiments of the present invention may be directed to oneor more of the problems set forth above.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 illustrates a block diagram of a processor-based system inaccordance with embodiments of the present invention;

FIG. 2 illustrates a block diagram of a memory management system inaccordance with embodiments of the present invention;

FIG. 3 illustrates a block diagram of a translation lookaside buffer inaccordance with embodiments of the present invention;

FIG. 4 illustrates a block diagram of a translation device in accordancewith embodiments of the present invention;

FIG. 5 illustrates a flow chart of a method for accessing a physicalmemory address when a memory management system receives a virtual memoryaddress in accordance with embodiments of the present invention; and

FIG. 6 illustrates a flow chart of a method for managing physical memoryaddress space of a computing system in accordance with embodiments ofthe present invention.

DETAILED DESCRIPTION

Some of the subsequently discussed embodiments may facilitate memorysystems with greater versatility, such as memory systems that usemultiple different types of memory devices and memory systems thatdynamically rearrange data stored on the different types of memorydevices. As is described in detail below, a memory management system mayinclude a table that correlates a physical memory address with a type ofmemory device. For example, a memory management system may include atable having multiple virtual memory addresses. Each virtual memoryaddress may correspond to a physical memory address and to data thatidentifies a type of corresponding memory device. The physical memoryaddress may be used to access the memory device when a table hit occurs.As such, the following discussion describes devices and methods inaccordance with embodiments of the present technique.

Turning now to the drawings, and referring initially to FIG. 1, a blockdiagram depicting a processor-based system, generally designated byreference numeral 10, is illustrated. The system 10 may be any of avariety of types such as a computer, pager, cellular phone, personalorganizer, control circuit, etc. In a typical processor-based device,one or more processors 12, such as a microprocessor, control theprocessing of system functions and requests in the system 10. As will beappreciated, the processor 12 may include an embedded North or Southbridge (not shown), for coupling components thereto. Alternatively, thesystem 10 may include separate bridges coupled between the processor 12and the various components of the system 10. As illustrated, theprocessor 12 may include cache 13 (e.g., CPU cache) to reduce theaverage time that it takes for the processor 12 to access memory.

Various devices may be coupled to the processor 12 depending on thefunctions that the system 10 performs. For instance, a user interfacemay be coupled to the processor 12. The user interface may includebuttons, switches, a keyboard, a light pen, a mouse, a display, and/or avoice recognition system, for instance. The display may include atouchscreen display, an LCD display, a CRT, LEDs, and/or an audiodisplay, for example. One or more communication ports may also becoupled to the processor 12. The communication port may be adapted to becoupled to one or more peripheral devices such as a modem, a printer, acomputer, or to a network, such as a local area network, remote areanetwork, intranet, or the Internet, for instance.

Because the processor 12 generally controls the functioning of thesystem 10 by implementing software programs, memory is operably coupledto the processor 12 to store and facilitate execution of variousprograms. Accordingly, a hierarchical memory system 14 is operablycoupled to the processor 12 via a system bus 16. The hierarchical memorysystem 14 includes a memory management system 18 and any number ofmemory devices. For example, the hierarchical memory system 14 mayinclude a memory_0 20 (e.g., of a first type), a memory_1 22 (e.g., of asecond type), and any additional memory devices represented by memory N24 (e.g., of an nth type).

The memory management system 18 may perform a variety of memorymanagement functions. For example, the memory management system 18 maymanage virtual memory address to physical memory address translation,memory reallocation, memory organization, memory usage, and so forth. Asillustrated, the memory management system 18 is operably coupled to thememory devices 20, 22, and 24 by respective data busses PA_0 26, PA_128, and PAN 30. As will be appreciated, PAN 30 may represent a number ofdata busses that correspond to the memory devices memory N 24.

One or more of the memory devices 20, 22, and 24 may be volatile memorywhich may include Dynamic Random Access Memory (DRAM), and/or StaticRandom Access Memory (SRAM). The volatile memory may include a number ofmemory modules, such as single inline memory modules (SIMMs), dualinline memory modules (DIMMs), and/or Hybrid Memory Cubes (HMCs). Aswill be appreciated, the volatile memory may simply be referred to asthe “system memory.” The volatile memory is typically quite large sothat it can store dynamically loaded applications and data.

Further, one or more of the memory devices 20, 22, and 24 may benon-volatile memory which may include read-only memory (ROM), such as anEPROM, flash memory (e.g., NOR and/or NAND), and/or phase-change memory(PCM) to be used in conjunction with the volatile memory. The size ofthe ROM is typically selected to be large enough to store any necessaryoperating system, application programs, and fixed data. Additionally,the non-volatile memory may include a high capacity memory such as atape or disk drive memory. Accordingly, the memory devices 20, 22, and24 do not need to be block storage devices.

As such, the hierarchical memory system 14 is versatile in allowing manytypes of memory devices 20, 22, and 24 to be operably coupled to theprocessor 12. Accordingly, the memory management system 14 may beadapted to the hierarchical memory system 14 to optimize the performanceof the memory devices 20, 22, and 24. Some examples of the memorymanagement system 18 adapted for use in the hierarchical memory system14 are illustrated in FIGS. 2-4. Specifically, FIG. 2 illustrates amemory management system 18 with a translate (XLAT) translation deviceand a translation lookaside buffer and FIGS. 3 and 4 further illustratethe translation lookaside buffer and the XLAT translation device,respectively. FIGS. 5 and 6 illustrate methods that the memorymanagement system 18 may use to manage the memory devices 20, 22, and24.

Referring now to FIG. 2, a block diagram of the memory management system18 is illustrated. During operation, the memory management system 18receives a virtual memory address 32 (e.g., from processor 12). Thememory management system 18 identifies a physical memory address 34 thatis mapped to the virtual memory address 32 and that is used to accessone of the memory devices 20, 22, and 24. If the memory managementsystem 18 is unable to identify which physical memory address 34 ismapped to the virtual memory address 32, then the memory managementsystem 18 produces (e.g., generates) a page fault 36, which may betransmitted to the processor 12.

To identify the physical memory address 34 that is mapped to the virtualmemory address 32, the memory management system 18 uses an XLATtranslation device 38 and a translation lookaside buffer (TLB) 40. TheXLAT translation device 38 and the TLB 40 may each store a respectivetable that maps virtual memory addresses to physical memory addresses.Although the XLAT translation device 38 and the TLB 40 are illustratedseparately, in certain embodiments, the XLAT translation device 38 andthe TLB 40 may be incorporated within a single device. As will beappreciated, the XLAT translation device 38 and the TLB 40 may containnon-overlapping data. For example, the XLAT translation device 38 maycontain table entries for a first portion of the virtual memoryaddresses, while the TLB 40 contains table entries for a second portionof the virtual memory addresses.

Typically, the TLB 40 contains table entries for virtual memoryaddresses that are accessed more frequently than the virtual memoryaddresses stored in the XLAT translation device 38. In certainembodiments, a search for the virtual memory address 32 may occurconcurrently in the XLAT translation device 38 and the TLB 40. In otherembodiments, a search for the virtual memory address 32 may occur in theTLB 40 before the search occurs in the XLAT translation device 38.However, after a table entry including the virtual memory address 32 isidentified (e.g., located), both the XLAT translation device 38 and theTLB 40 stop searching for the virtual memory address 32.

In the present embodiment, the XLAT translation device 38 and the TLB 40may each store data relating to how frequently a particular virtualmemory address and/or physical memory address are accessed. Further, theXLAT translation device 38 and the TLB 40 may each store data thatidentifies a type of memory device corresponding to the physical memoryaddress. Using this additional data, the memory management system 18 mayoptimize memory usage and/or optimize table mapping data stored in theXLAT translation device 38 and the TLB 40, as explained in detail below.

Accordingly, FIG. 3 illustrates a block diagram of the TLB 40 that maystore data relating to how frequently a particular virtual memoryaddress and/or physical memory address are accessed, and may store datathat identifies a type of memory device corresponding to the particularphysical memory address. In certain embodiments, the TLB 40 may be acontent-addressable memory (CAM) device or n-way associative memorydevice. Specifically, the TLB 40 stores a table 42 having rows 44 andcolumns (46-52). In the present embodiment, each row 44 relates to aseparate table entry. As such, each row 44 includes a virtual memoryaddress column 46, a physical memory address column 48, a least recentlyused (LRU) column 50, and a device identification (TYPE) column 52.

The virtual memory address column 46 includes a listing of all virtualmemory addresses contained in the TLB 40. Further, the physical memoryaddress column 48 includes a physical memory address in each row 42 thatcorresponds to the virtual memory address in the virtual memory addresscolumn 46 of the respective row 42. The LRU column 50 includes data thatrelates to how frequently a respective physical memory address isaccessed (e.g., access or usage data). For example, the LRU column 50may include a value that represents the total number of times itscorresponding virtual memory address and/or physical memory address havebeen accessed. As such, the LRU column 50 may be used to identifywhether table entries should be removed from the table 42. For example,rows 44 that have been accessed with the least frequency (e.g., have thelowest value stored in the LRU column 50), may be removed from the table42.

The TYPE column 52 includes device identification data in each row 42that identifies a type of device that corresponds to the physical memoryaddress in the physical memory address column 48 of the respective row42. The device is accessed using the physical memory address (e.g., whena table hit occurs). For example, the device identification data may bea value that corresponds to a type of device. As will be appreciated,the memory management system 18 may include data that corresponds toeach device. For example, the memory management system 18 may includedata such as a name of each device, an operating speed of each device, abus assigned to each device, an indication of relative speed of eachdevice in relation to other physical devices, an endurance of eachdevice, and so forth. During operation, the physical address may be usedto directly access the memory devices 20, 22, and 24, thereby quicklyaccessing data stored on the memory devices 20, 22, and 24.

Turning to FIG. 4, a block diagram of the XLAT translation device 38 isillustrated. The XLAT translation device 38 includes a translation table(XT) 54 that may store data relating to how frequently a particularvirtual memory address and/or physical memory address are accessed, andmay store data that identifies a type of the memory device thatcorresponds with each physical memory address. Further, the XLATtranslation device 38 includes a control unit 56 (e.g., a logic die of ahybrid memory cube) for controlling various operations of the XLATtranslation device 38. Specifically, the XT 54 stores a table havingrows 58 and columns (60-66). In the present embodiment, each row 58relates to a separate table entry. As such, each row 58 includes avirtual memory address column 60, a physical memory address column 62,an LRU column 64, and a TYPE column 66.

The virtual memory address column 60 includes a listing of all virtualmemory addresses contained in the XT 54. Further, the physical memoryaddress column 62 includes a physical memory address in each row 58 thatcorresponds to the virtual memory address in the virtual memory addresscolumn 60 of the respective row 58. The LRU column 64 includes data thatrelates to how frequently a respective physical memory address isaccessed (e.g., access or usage data). For example, the LRU column 64may include a value that represents the total number of times itsrespective virtual memory address and/or physical memory address havebeen accessed. As such, the LRU column 64 may be used (e.g., by thecontrol unit 56 of the translation device 38) to identify whether tableentries should be moved from the XT 54 to the TLB 40. For example, rows58 that have been accessed with the highest frequency (e.g., have thehighest value stored in the LRU column 64), may be moved from the XT 54into the TLB 40, at least in some conditions.

The TYPE column 66 includes device identification data in each row 58that identifies a type of device that corresponds to the physical memoryaddress in the physical memory address column 62 of the respective row58. The device is accessed using the physical memory address (e.g., whena table hit occurs). For example, the device identification data may bea value that corresponds to a type of device. During operation, thephysical memory address may be used to directly access the memorydevices 20, 22, and 24, thereby quickly accessing data stored on thememory devices 20, 22, and 24.

The XLAT translation device 38 may be any of a variety of differentdevices, such as a hybrid memory cube (HMC) or a pattern recognitiondevice, such as that disclosed in U.S. Publication Number 2010/0138575.Furthermore, hardware (e.g., processor) and/or software may be used toexecute a search of the XT 54. As will be appreciated, prolonged accessto the XT 54 may result in a significant performance penalty,particularly if stored in main memory (e.g., where the translationdevice 38 itself serves as the main memory, as may be the case ifembodied in an HMC device). Accordingly, certain translation devices 38may include hardware and/or software logic in addition to memory cells.For example, the XT 54 may be stored on a high performance memory array(HPMA) (e.g., HMC) or an assistive search memory device, such as thepreviously mentioned pattern recognition device. Such devices may beconfigured to search for virtual memory addresses within the XT 54(e.g., execute a table walk). It should be noted that the TLB 40 mayalso be stored on an HPMA or an assistive search memory device. Incertain embodiments, the TLB 40 and the XT 54 may be stored on the samedevice. By using an HPMA or an assistive search memory device, improvedperformance may be achieved. In certain embodiments, the control unit 56may be used to perform a variety of functions. For example, the controlunit 56 may control page table walks, TLB updates, LRU calculations, LRUupdates, direct memory access for page movements, dynamicallyrearranging data that is assigned to the devices, dynamically change themapping of virtual memory addresses to physical memory addresses, and soforth.

The control unit 56 may include software and/or hardware to aidfunctions of the memory management system 18. As such, FIG. 5illustrates a flow chart of a method 68 for accessing a physical memoryaddress when the memory management system 18 receives a virtual memoryaddress. At block 70, the memory management system 18 receives a virtualmemory address. Then, at block 72, the memory management system 18searches for the virtual memory address in the TLB 40 (e.g., performs alookup). Next, at block 74, a determination is made as to whether thememory management system 18 has identified (e.g., found) the virtualmemory address in the TLB 40. If there is a TLB “miss,” at block 76, thememory management system 18 searches for the virtual memory address inthe XT 54 (e.g., executes a lookup or a table walk). Then, at block 78,a determination is made as to whether the memory management system 18has identified the virtual memory address in the XT 54. If there is anXT “miss,” at block 80, the memory management system 18 generates a pagefault 36 which is sent to the processor 12.

If there is an XT “hit,” then, at block 82, the memory management systemmoves the XT table entry to the TLB 40. Further, at block 82, the memorymanagement system 18 moves the least used TLB 40 entry to the XT 54.Next, at block 84, the memory management system 18 translates thevirtual memory address to a physical memory address. This occurs afterblock 82, or in response to a TLB “hit” occurring per block 74. As willbe appreciated, translating the virtual memory address to the physicalmemory address may include accessing all of the data in the entry thatrelates to the virtual memory address. For example, the memorymanagement system 18 may retrieve the TYPE column data from the tableentry for accessing the memory device. At block 86, the LRU data for theaccessed table entry is updated (e.g., modified). For example, the valuestored in the LRU column may be increased by one. Next, at block 88, thephysical memory address is accessed.

Turning now to FIG. 6, a flow chart 90 of a method for managing a memoryaddress space of a computing system is illustrated. At block 92, thememory management system 18 may use LRU data to rank table entries, suchas ranking a table entry based on a number of times that a virtualmemory address and/or a physical memory address of the table entry isaccessed. Next, at block 94, the memory management system 18 mayidentify table entries that have a greater amount of use than othertable entries and/or the memory management system 18 may identify tableentries that have a lower amount of use than other table entries. Then,at block 96, the memory management system 18 may compare the type ofmemory devices that are allocated to the identified entries to availabletypes of memory devices. For example, the memory management system 18may identify whether table entries with a greater amount of use (e.g.,higher access rates) are allocated to better memory types (e.g., fastermemory, improved endurance) than table entries with a lower amount ofuse. At block 98, the memory management system 18 may identify whetherthere is a mismatch between a number of times the physical memoryaddress is accessed and a type of memory device corresponding to thephysical memory address.

If there is not a mismatch, the method may return to block 92. However,if there is a mismatch between the number of times the physical memoryaddress is accessed and the type of memory device corresponding to thephysical memory address, the memory management system 18 may identifywhether a memory swap can be performed, per block 100. In certainembodiments, a memory swap may include exchanging a first set of datastored in a first type of memory with a second set of data stored in asecond type of memory. For example, the memory management system 18 maymove a first set of data stored in a first type of memory to a secondtype of memory and move a second set of data stored in the second typeof memory to the first type of memory. Furthermore, moving the first andsecond sets of data may happen concurrently. For example, certain typesof memory may support data movement that occurs simultaneously in bothdirections, such as DRAM DIMMs and HMC, and DRAM DIMMs and PCM. If amemory swap cannot be performed, the memory management system 18 mayidentify whether there is any memory available for moving the mismatcheddata, per block 102. If there is not any memory available, the methodmay return to block 100.

If there is memory available, per block 104, the memory managementsystem 18 may move data from the memory of the identified entries to theavailable memory. For example, the memory management system 18 may causedata that corresponds to the identified table entries to be moved to adifferent type of memory device to remove the mismatch between thenumber of times the physical memory address is accessed and the type ofmemory corresponding to the physical memory address. Returning to block100, if the memory management system 18 is able to perform a memoryswap, the memory management system 18 may swap data between the memorydevices, per block 106. After block 104 or block 106, the memorymanagement system 18 updates the TLB 40 and/or XT 54 table entries. Forexample, the memory management system 18 may update the TLB 40 and/or XT54 table entries with a revised mapping between a virtual memory addressand a physical memory address, revised device data, and/or updated LRUdata.

While the blocks 92 thorough 108 are described as being performed by thememory management system 18, it should be noted that any portion of thememory management system 18 (e.g., hardware and/or software) may performthe items described. For example, any of blocks 92 thorough 108 may beperformed by the control unit 56. In certain embodiments, the memorymanagement system 18 and/or the control unit 56 may be configured todynamically change the mapping of virtual memory addresses to physicalmemory addresses based on an endurance or speed of a memory type. Usingthe techniques described herein, the memory management system 18 maymaximize the performance of the system 10 and/or minimize softwareoverhead.

While the invention may be susceptible to various modifications andalternative forms, specific embodiments have been shown by way ofexample in the drawings and have been described in detail herein.However, it should be understood that the invention is not intended tobe limited to the particular forms disclosed. Rather, the invention isto cover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the followingappended claims.

What is claimed is:
 1. A memory management system comprising: a firstmemory comprising a first plurality of devices and configured to store afirst translation table, wherein the first memory is configured toretrieve data stored in the first translation table according to a firstspeed based on operation of the first plurality of devices; and a secondmemory comprising a second plurality of devices and configured to storea second translation table, wherein the second memory is configured toretrieve data stored in the second translation table according to asecond speed based on operation of the second plurality of devices,wherein the second memory and the first memory are configured toexchange a first table entry of the first translation table with asecond table entry of the second translation table based on an accesspattern, and wherein the access pattern indicates how frequently thefirst table entry was accessed relative to at least a third table entry.2. The memory management system of claim 1, comprising: a controllerconfigured to: determine that a first set of data is accessed more oftenthan a second set of data; perform a memory swap to exchange the firstset of data stored in a first type of memory with a second set of datastored in a second type of memory; and update corresponding tableentries for the first set of data and the second set of data with arevised mapping between a virtual memory address and a physical memoryaddress, revised device data, updated least recently used (LRU) data. 3.The memory management system of claim 2, wherein the controller isconfigured to move the first set of data and the second set of dataconcurrently.
 4. The memory management system of claim 2, wherein thesecond type of memory is characterized by operating speeds greater thanthe first type of memory.
 5. The memory management system of claim 1,wherein: the first translation table stores indications of anassociation between a first virtual memory address, a first physicalmemory address, first data that indicates how frequently the firstphysical memory address is accessed, and second data that identifies afirst memory type of a first memory device comprising the first physicalmemory address, and the second translation table stores indications ofan association between a second virtual memory address, a secondphysical memory address, third data that indicates how frequently thesecond physical memory address is accessed, and fourth data thatidentifies a second memory type of a second memory device comprising thesecond physical memory address; and a control unit configured to controloperation of the first memory device and the second memory device basedat least in part on the first translation table and the secondtranslation table.
 6. The memory management system of claim 1, whereinthe first translation table and the second translation table comprisenon-overlapping data.
 7. The memory management system of claim 1,wherein a hybrid memory cube or pattern recognition device comprises thefirst memory and the second memory.
 8. The memory management system ofclaim 1, comprising: a translation lookaside buffer configured to storethe first translation table, wherein the first memory comprises thetranslation lookaside buffer; and a hybrid memory cube or patternrecognition device configured to store the second translation table,wherein the second memory comprises the hybrid memory cube or patternrecognition device.
 9. The memory management system of claim 1,comprising a controller configured to search the first translation tableand the second translation table concurrently.
 10. A method comprising:receiving a virtual memory address; searching a first translation tablefor the virtual memory address; searching a second translation table forthe virtual memory address after searching the first translation table;and moving an entry from the second translation table corresponding tothe virtual memory address to the first translation table.
 11. Themethod of claim 10, comprising moving an entry from the secondtranslation table corresponding to the virtual memory address to thefirst translation table stored in a translation lookaside buffer. 12.The method of claim 10, wherein searching the first translation tablefor the virtual memory address comprises searching indications stored inthe first translation table, wherein the indications associaterespective virtual memory addresses with a respective physical memoryaddress, respective first data that indicates how frequently therespective physical memory address is accessed, and respective seconddata that identifies a respective memory type from a plurality of memorytypes corresponding to a memory device referenced by the respectivephysical memory address.
 13. The method of claim 10, wherein searchingthe first translation table for the virtual memory address comprisessearching indications stored in the first translation table viacommunication with a translation lookaside buffer.
 14. The method ofclaim 10, wherein searching the second translation table for the virtualmemory address comprises searching indications stored in the secondtranslation table via communication with a translation device, whereinthe indications comprise second data that indicates how frequently asecond physical memory address is accessed.
 15. The method of claim 10,wherein moving the entry from the second translation table correspondingto the virtual memory address to the first translation table comprises:identifying first data for the virtual memory address stored in thesecond translation table; identifying second data from the firsttranslation table for a least accessed physical memory address;determining to swap storage locations within the first translation tableand the second translation table by exchanging the entry correspondingto the first data with an additional entry corresponding to the seconddata; and moving the entry from the second translation table to thefirst translation table and moving the additional entry from the firsttranslation table to the second translation table.
 16. A method formanaging a memory address space of a computer system comprising:identifying that a table entry in a first translation table correspondsto a virtual memory address that was accessed a number of times lessthan a threshold number of accesses; determining to change a type ofmemory device corresponding to the virtual memory address in response toidentifying that the table entry indicates that the virtual memoryaddress was accessed less than the threshold number of accesses; and inresponse to determining to change the type of memory device,deallocating a first physical memory address of a first memory devicefrom the virtual memory address and allocating a second physical memoryaddress to the virtual memory address, wherein the second physicalmemory address corresponds to an allocation of a portion of a secondmemory device for the virtual memory address.
 17. The method of claim16, comprising determining to allocate the second physical memoryaddress to the virtual memory address based at least in part on relativememory speeds of the second memory device and the first memory device.18. The method of claim 16, comprising: searching a second translationtable for the table entry indicating the virtual memory address beforeidentifying that the table entry in the first translation tablecorresponds to the virtual memory address accessed the number of timesless than the threshold number of accesses; and moving an entry from thesecond translation table corresponding to the virtual memory address tothe first translation table in response to identifying that the tableentry indicates that the virtual memory address was accessed less thanthe threshold number of accesses.
 19. The method of claim 16, whereinthe first memory device and the second memory device comprise differentmemory types.
 20. The method of claim 16, comprising: receiving anindication to search for an additional table entry; determining thatneither of the first translation table or a translation lookup buffercomprise the additional table entry; and generating a page fault inresponse to determining that neither of the first translation table orthe translation lookup buffer comprise the additional table entry.